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fujitsu microelectronics data sheet copyright?2009 fujitsu microelectro nics limited all rights reserved 2009.1 assp for power management applications (general-purpose dc/dc converter) 2ch dc/dc converter ic with synchronous rectification mb39a138 description mb39a138 is a 2ch step-down dc/dc converter equi pped with a bottom detection comparator and n-ch/ n-ch synchronous rectification. it s upports low on-duty operation to allow st able output of low voltages when there is a large difference between input and output voltages. mb39a138 realizes ultra-rapid response and high efficiency with built-in enhanced protection features. features ? high efficiency high accurate reference voltage : 1.0 % (indoor temperature ) input voltage range : 6 v to 24 v output voltage setting range : ch1 0.7 v to 5.2 v : ch2 2.0 v to 5.2 v built-in diode for boot strap built-in over voltage protection function built-in under voltage protection function built-in over current detection function built-in over temperature protection function built-in soft-start circ uit without load dependence built-in discharge control circuit built-in synchronous rectification ty pe output steps for n-ch mos fet standby current : 0 a (typ) small package : tssop-24 applications digital tv photocopiers stb bd, dvd players/recorders projectors various other advanced devices ds04?27270?1e
mb39a138 2 ds04?27270?1e pin assignment (top view) (fpt-24p-m10) 24 23 22 21 20 19 18 17 16 15 14 13 cb1 drvh1 lx1 drvl1 vcc vb pgnd drvl2 lx2 drvh2 cb2 test 1 2 3 4 5 6 7 8 9 10 11 12 ctl1 cs1 fb1 vo1 ilim1 gnd cvblpf ctl2 ilim2 vo2 fb2 cs2
mb39a138 ds04?27270?1e 3 pin descriptions pin no. pin name i/o description 1 ctl1 i ch1 control pin. 2 cs1 i ch1 start time setting capacitor connection pin. 3 fb1 i ch1 feedback pin for dc/dc output voltage. 4 vo1 i ch1 input pin for dc/dc output voltage. 5 ilim1 i ch1 over current detection level setting voltage input pin. 6gnd ? ground pin. 7 cvblpf i control circuit bias input pin. 8 ctl2 i ch2 control pin. 9 ilim2 i ch2 over current detection level setting voltage input pin. 10 vo2 i ch2 input pin for dc/dc output voltage. 11 fb2 i ch2 feedback pin for dc/dc output voltage. 12 cs2 i ch2 soft-start time setting capacitor connection pin. 13 test i pin for ic test. connect to gnd in the dc/dc operation. 14 cb2 ? ch2 connection pin for boot strap capacitor. 15 drvh2 o ch2 output pin for external high-side fet drive. 16 lx2 ? ch2 inductor and external high-side fet source connection pin. 17 drvl2 o ch2 output pin for external low-side fet gate drive. 18 pgnd ? ground pin for output circuit. 19 vb o output circuit bias output pin. 20 vcc i power supply pin for refer ence voltage and control circuit. 21 drvl1 o ch1 output pin for external low-side fet gate drive. 22 lx1 ? ch1 inductor and external high-side fet source connection pin. 23 drvh1 o ch1 output pin for exter nal high-side fet gate drive. 24 cb1 ? ch1 connection pin for boot strap capacitor.
mb39a138 4 ds04?27270?1e block diagram 3 4 vo1 fb1 /ctl1 uvp,otp 5 a vo control intref1 2 c s 1 /ctl1,/uvlo uvp,otp ovp_ q 1 5 ilim1 intref1 x 1.15 v intref1 x 0.7 v u vp_ q 1 11 10 vo2 fb2 9 ilim2 12 c s 2 6 gnd cb2 drvh2 drvl2 lx2 17 16 15 14 b i as 7 cvblpf uvlo h:uvlo rele as e otp 50 s del a y 1.7 m s del a y r s q r s q ovp_ q 2 u vp_ q 2 drive logic r s q lx1 pgnd 10 a t on gener a tor vo1 vcc vcc 24 (5.2 v) 19 5.2 v reg. vb cb1 20 ref ctl 8 ctl2 1 ctl1 drv-1 drv-2 1 8 21 22 2 3 pgnd drvh1 drvl1 lx1 b i as ? + + ? + ? + ? + ? + the configuration of a control circ uit is the same as that of ch1.
mb39a138 ds04?27270?1e 5 absolute maximum ratings warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol condition rating unit min max power supply voltage v vcc ?? 26 v cb pin input voltage v cb cb1, cb2 pins ? 32 v lx pin input voltage v lx lx1, lx2 pins ? 26 v voltage between cb and lx v cblx ?? 7v control input voltage v i ctl1, ctl2 pins ? 26 v input voltage v cvblpf cvblpf pin ? vb + 0.3 v v fb fb1, fb2 pins ? vb + 0.3 v v vo vo1, vo2 pins ? vb + 0.3 v v cs cs1, cs2 pins ? vb + 0.3 v v ilim ilim1, ilim2 pins ? vb + 0.3 v v test test pin ? vb + 0.3 v output current i out drvh1, drvh2 pins, drvl1, drvl2 pins ? 60 ma power dissipation p d ta + 25 c ? 1333 mw storage temperature t stg ? ? 55 + 125 c
mb39a138 6 ds04?27270?1e recommended operating conditions warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application out side the listed conditions are advised to contact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage v vcc ? 6 ? 24 v cb pin input voltage v cb ??? 30 v bias output current i vb ? ? 1 ?? ma ctl pin input voltage v i ctl1, ctl2 pins 0 ? 24 v input voltage v cvblpf cvblpf pin 0 ? vb v v fb fb1, fb2 pins 0 ? vb v v vo vo1, vo2 pins 0 ? vb v v ilim ilim1, ilim2 pins 30 ? 200 mv peak output current i out drvh1, drvh2 pins, drvl1, drvl2 pins duty 5 % (t = 1/f osc duty) ? 1200 ? + 1200 ma soft start capacitor c cs ?? 0.018 ? f cb pin capacitor c cb ?? 0.1 1.0 f bias voltage output capacitor c vb ?? 2.2 10.0 f bias voltage input capacitor c cvblpf ?? 1.0 4.7 f operating ambient temperature ta ? ? 30 + 25 + 85 c
mb39a138 ds04?27270?1e 7 electrical characteristics (ta = + 25 c, vcc pin = 12 v, ctl1, ctl2 pins = 5 v = cvblpf pin : vb pin connected ) (continued) parameter sym- bol pin no. condition value unit min typ max bias voltage block [vb reg.] output voltage v vb 19 ? 5.04 5.20 5.36 v input stability line 19 vcc pin = 6 v to 24 v ? 10 100 mv load stability load 19 vb pin = 0 a to ? 1 ma ? 10 100 mv short-circuit output current i os 19 vb pin = 0 v ? 200 ? 140 ? 100 ma under voltage lockout protection circuit block [uvlo] threshold voltage v tlh 7 cvblpf pin 4.0 4.2 4.4 v v thl 7 cvblpf pin 3.4 3.6 3.8 v hysteresis width v h 7 cvblpf pin ? 0.6* ? v soft-start/ discharge block [soft-start, discharge] charge current i cs 2, 12 cs1, cs2 pins = 0 v ? 7.1 ? 5.0 ? 3.8 a electrical discharge resistance r d 4, 10 ctl1, ctl2 pins = 0 v, vo1, vo2 pins = 0.5 v ? 35 70 ? discharge end voltage v vovth 4, 10 ctl1, ctl2 pins = 0 v, vo1, vo2 pins 0.1 0.2 0.3 v on/off time generator block [ton generator] on time t on11 23 vcc pin = 12 v, vo1 pin = 1.2 v 256 320 384 ns t on12 15 vcc pin = 12 v, vo2 pin = 3.3 v 470 587 704 ns minimum on time t onmin 23, 15 vcc pin = 12 v, vo1, vo2 pins = 0 v ? 100 ? ns minimum off time t offmin 23, 15 ?? 380 ? ns output voltage block [vo control, error comp.] feedback voltage (ch1) v th1 3ta = + 25 c 0.693 0.700 0.707 v v tht1 3ta = 0 c to + 85 c 0.690* ? 0.710* v feedback voltage (ch2) v th2 11 ta = + 25 c 1.980 2.000 2.020 v v tht2 11 ta = 0 c to + 85 c 1.970* ? 2.030* v bottom detection voltage (ch1) v th3 4ta = + 25 c 1.202 1.226 1.250 v v tht3 4ta = 0 c to + 85 c 1.196 ? 1.256 v bottom detection voltage (ch2) v th4 10 ta = + 25 c 3.381 3.450 3.519 v v tht4 10 ta = 0 c to + 85 c 3.364 ? 3.536 v fb pin input current i fb 3, 11 fb1, fb2 pins = 0.8 v ? 0.1 0 + 0.1 a vo pin input current i vo1 4 vo1 pin = 1.226 v ? 80 115 a i vo2 10 vo2 pin = 3.450 v ? 225 325 a over-volt- age protection circuit block [ovp comp.] over-voltage detecting voltage v ovp 3, 11 (4, 10) error comp. input intref 1.11 intref 1.15 intref 1.19 v over-voltage detection time t ovp 3, 11 (4, 10) ?? 50 ? s
mb39a138 8 ds04?27270?1e (ta = + 25 c, vcc pin = 12 v, ctl1, ctl2 pins = 5 v = cvblpf pin : vb pin connected) (continued) parameter sym- bol pin no. condition value unit min typ max under-volt- age protec- tion circuit block [uvp comp.] under-volt- age detect- ing voltage v uvp 3, 11 (4, 10) error comp. input intref 0.65 intref 0.70 intref 0.75 v under-volt- age detec- tion time t uvp 3, 11 (4, 10) ? 1.2* 1.7* 2.2* ms over-tem- perature protection circuit block [otp] protection tempera- ture t otph ? ? ? + 150* ? c t otpl ? ? ? + 125* ? c output block [drv] high-side output on- resistance r oh 23, 15 drvh1, drvh2 pins = ? 100 ma ? 57 ? r ol 23, 15 drvh1, drvh2 pins = 100 ma ? 1.5 2.5 ? low-side output on- resistance r oh 21, 17 drvl1, drvl2 pins = ? 100 ma ? 46 ? r ol 21, 17 drvl1, drvl2 pins = 100 ma ? 12 ? output source current i source 23, 15 lx1, lx2 pins = 0 v, cb1, cb2 pins = vb drvh1, drvh2 pins = 2.5 v duty 5% ?? 0.4* ? a 21, 17 lx1, lx2 pins = 0 v, cb1, cb2 pins = vb drvl1, drvl2 pins = 2.5 v duty 5% ?? 0.5* ? a output sink current i sink 23, 15 lx1, lx2 pins = 0 v, cb1, cb2 pins = vb drvh1, drvh2 pins = 2.5 v duty 5% ? 0.7* ? a 21, 17 lx1, lx2 pins = 0 v, cb1, cb2 pins = vb drvl1, drvl2 pins = 2.5 v duty 5% ? 0.9* ? a dead time t d 23, 21 15, 17 lx1, lx2 pins = 0 v, cb1, cb2 pins = vb pin drvl1, drvl2 pins-low to drvh1, drvh2 pins-on ? 40 ? ns lx1, lx2 pins = 0 v, cb1, cb2 pins = vb pin drvh1, drvh2 pins-low to drvl1, drvl2 pins-on ? 80 ? ns diode voltage v f 24, 14 i f = 10 ma 0.7 0.8 0.9 v leak current i leak 24, 14 cb1, cb2 pins = 30 v, lx1, lx2 pins = 24 v ta = + 25 c ? 0.1 1 a
mb39a138 ds04?27270?1e 9 (continued) (ta = + 25 c, vcc pin = 12 v, ctl1, ctl2 pins = 5 v = cvblpf pin : vb pin connected) * : this parameter is not be specifi ed. this should be used as a refer ence to support designing the circuits. parameter sym- bol pin no. condition value unit min typ max over current detection block [current sense] ilim pin source current i ilim 5, 9 ilim1, ilim2 pins = 0.1 v, ta = + 25 c ? 12.5 ? 10.0 ? 8.3 a ilim pin source current tempera- ture slope t ilim 5, 9 ta = + 25 c (reference) ? 4200* ? ppm / c over current detection offset voltage v offilim 5, 9 ilimx ? (pgnd ? lxx) pgnd ? lxx = 60 mv ? 20 0 + 20 mv over current detection setting range v ilim 5, 9 ilim pin input range 30 ? 200 mv control block [ctl1, ctl2] on condition v on 1, 8 ctl1, ctl2 pins 2 ? 24 v off condition v off 1, 8 ctl1, ctl2 pins 0 ? 0.8 v hysteresis width v h 1, 8 ctl1, ctl2 pins ? 0.4* ? v input current i ctlh 1, 8 ctl1, ctl2 pins = 5 v ? 25 40 a i ctll 1, 8 ctl1, ctl2 pins = 0 v ? 01 a general standby current i ccs 20 ctl1, ctl2 pins = 0 v ? 010 a power supply current i cc 20 lx1, lx2 pins = 0 v, fb1, fb2 pins = 1.0 v ? 1.5 2.0 ma
mb39a138 10 ds04?27270?1e typical characteristics (continued) vb bias voltage vs. operating ambient temperature vb bias voltage vs. vb bias output current vb bias voltage v vb (v ) vb bias voltage v vb (v) operating ambient temperature ta ( c) vb bias output current (ma) error comp.1 threshold voltage vs. operating ambient temperature error comp.2 threshold voltage vs. operating ambient temperature error comp.1 threshold voltage v tht1 (v) error comp.2 threshold voltage v tht2 (v) operating ambient temperature ta ( c) operating ambient temperature ta ( c) 0 500 1000 1500 2000 ? 50 -25 0 +25 +50 +75 +100 +125 1 333 power dissipation vs. operating ambient temperature power dissipation p d (mw) operating ambient temperature ta ( c) 5.00 5.04 5.0 8 5.12 5.16 5.20 5.24 5.2 8 5. 3 2 5. 3 6 5.40 -40 -20 0 +20 +40 +60 + 8 0 +100 vcc = 12 v i vb = 0 a 5.0 5.1 5.2 5. 3 5.4 0 5 10 15 20 25 3 0 t a = +25 c vcc = 6 v vcc = 12 v vcc = 24 v 0.690 0.692 0.694 0.696 0.69 8 0.700 0.702 0.704 0.706 0.70 8 0.710 -40 -20 0 +20 +40 +60 + 8 0 +100 1.97 1.9 8 1.99 2.00 2.01 2.02 2.0 3 -40 -20 0 +20 +40 +60 + 8 0 +100
mb39a138 ds04?27270?1e 11 (continued) drvh1 on time vs. operating ambient temperature drvh2 on time vs. operating ambient temperature drvh1 on time t on11 (ns) drvh2 on time t on12 (ns) operating ambient temperature ta ( c) operating ambient temperature ta ( c) minimum off time vs. operating ambient temperature minimum off time vs. input voltage minimum off time t offmin (ns) minimum off time t offmin (ns) operating ambient temperature ta ( c) input voltage v in (v) dead time vs. operating ambient temperature bootstrup diode i f vs. v f dead time (ns) i f current i f (ma) operating ambient temperature ta ( c) v f voltage v f (v) 260 2 8 0 3 00 3 20 3 40 3 60 38 0 400 -40 -20 0 +20 +40 +60 + 8 0 +100 vcc = 12 v vo1 = 1.2 v 460 500 540 5 8 0 620 660 700 740 -40 -20 0 +20 +40 +60 + 8 0 +100 vcc = 12 v vo2 = 3 . 3 v 200 250 3 00 3 50 400 450 500 550 600 -40 -20 0 +20 +40 +60 + 8 0 +100 vcc = 12 v 200 250 300 350 400 450 500 550 600 510152025 ta = +25 20 40 60 8 0 100 120 -40 -20 0 +20 +40 +60 + 8 0 +100 lx = 0 v v cb = vb t d 1 t d 2 0 5 10 15 20 25 30 0.2 0.4 0.6 0.8 1 1.2 ta = ? = + = +
mb39a138 12 ds04?27270?1e function 1. bottom detection comparator system the bottom detection comparator system uses fixed on time (t on ) and the switching ripple voltage which superimposed the output voltage (v out ). the t on time is uniquely defined by the power supply voltage (v in ) and the output voltage (v out ). during the t on period, a current is supplied from the power supply voltage (v in ). this results in an increased inductor current (i lx ) and also an increased output voltage (v out ) due to the parasitic resist ance (esr) of the output capacitor. and when the t off period arrives, the energy accumulated in th e inductor is supplied to the load to decrease the inductor current (i lx ) gradually. consequently, the output voltage (v out ), which has been increasing due to the parasitic resistance (esr) of the output capa citor, also decreases. when the output voltage is below a certain level, rs-ff is set and the t on period arrives again. switching is repeated as described above. error comp. is used to compare the reference voltage (intref) with the output period voltage v fb to control the off-duty condition in orde r to stabilize the output voltage. bias t on generator drive logic intref v in i lx s v out bias reg. lo-side drive fb ? + rs-ff rq hi-side drive rs out err out v in v out esr drvh drvl ton toff intref fb i lx rs out drvh
mb39a138 ds04?27270?1e 13 (1) bias voltage block (vb reg.) it outputs 5.2 v (typ) for setting of the output ci rcuit's power supply and the bootstrap voltage. the bias power supply is supplied from the cvbl pf pin (pin 7) to the control ci rcuit, which is smoothed with the rc filter of the resistor and the capac itor connected outside of the ic. (2) under voltage lockout pr otection circuit block (uvlo) a bias voltage (v cvblpf ) of the control ic, a transitional state at st artup, or a sudden drop leads to malfunction of the control ic, causing system destruction/deterior ation. to prevent such malfunction, the under voltage lockout protection circuit detects a voltage drop at the cvblpf pin (pin 7) and fixes drvh1 pin (pin 23), drvh2 pin (pin 15) and drvl1 pin (pin 21), drvl2 pin (pin 17) to the "l" level. when voltages at the cvblpf pin exceed the threshold vo ltage of the under voltage lockout pr otection circuit, the system is restored. (3) soft-start/discharge block (soft-start, discharge) the soft-start block is the circuit to pr event a rush current when turning power on. when the ctl1 pin (pin 1) and ctl2 pi n (pin 8) are set to the "h" level, the capacitor connected to the cs1 pin (pin 2) and, cs2 pin (pin 12) starts charging and it s lamp voltage is input to the error comparator (error comp.) of each channel. this allows for the setting of the soft-start time that does not depend on the output load of the dc/dc converter. the discharge block is the circuit to discharge electrical charges stored in an output capacitor at output stop. when setting the ctl1 pin (pin 1) and the ctl2 pin (pin 8) "l" level, fet for discharge (r on = 35 ? (typ)) which is connected between the vo1 pin (pin 4), vo2 pi n (pin 10), and gnds w ill turn on and discharge the output capacitors. when vo1 pin voltage and vo2 pin vo ltage go down below 0.2 v (typ) after discharging starts, fet for discharge is turned off and the dischar ge operation stops. also, the discharge block works when detecting low voltage at the under-voltage protection circuit block (uvp comp.) and detecting ic junction temperature increase at the over-t emperature protection circuit block (otp). (4) on/off time generator block (t on generator) the on/off time generator block (t on generator) contains a capacitor for timing setting and a resistor for timing setting and generates on time which depends on input voltage and output voltage. on time for each ch is obtained by the following formula. the oscillation frequency of ch2 is set to 1.5 times that of ch1 to prevent the beat by the frequency difference among channels. t on11 (ns) = v vo1 3200 (f osc1 310 khz) v vcc t on12 (ns) = v vo2 2133 (f osc2 465 khz) v vcc
mb39a138 14 ds04?27270?1e (5) output voltage setting block (vo control, error comp.) the output voltage setting block (vo control, error co mp.) detects the bottom value of ripple voltage that superimposed output voltage for dc/dc converter at the error comparator. the optional output voltage can be set by connecting the external outp ut voltage setting resistor to the fb1 pi n (pin 3) and the fb2 pin (pin 11). also, the output setting resistor of the built-in ic c an be used by connecting the fb1 pin and the fb2 pin to the cvblpf pin (pin 7). output voltage setting table (6) over-voltage protection circuit block (ovp comp.) it compares 1.15 times (typ) of the internal refere nce voltage intref (ch1/ch2: 0.7v/2.0v) with the feedback voltage that is input to the fb1 pin (pin 3) and the fb2 pin (pin 11). t he rs latch is set and the drvh1 pin (pin 23) and the drvh2 pin (pin 15) set to "l" level and the drvl1 pin (pin 21) and the drvl2 pin (pin 17) set to "h" level, when the feedback voltage detects a higher state at 50 s (typ) or more. the voltage output stops to fixes the high-side fet to the off-state and the low-side fet to the on-state, of both channels in the dc/dc converter. the over-voltage protection state can be cancelled by setting the ic to st andby state first and then resetting the latch using the uvlo signal. (7) under-voltage protection circuit block (uvp comp.) it compares 0.7 times (typ) of the internal referenc e voltage intref (ch1/ch2: 0.7v/2.0v) with the feedback voltage that is input to the fb1 pin (pin 3) and the fb2 pin (pin 11). t he rs latch is set and the drvh1 pin (pin 23) and the drvh2 pin (pin 15) go to "l" level and the drvl1 pin (pin 21) and the drvl2 pin (pin 17) go to "l" level, when the feedback voltage detects a lower state at 1.7 ms (typ) or more. the discharge function internal in the ic operat es and the voltage output of both chan nels stops, in synchronization with setting the latch of under voltage protection. the under-voltage protection state can be cancelled by se tting the ic to standby stat e first and then resetting the latch using the uvlo signal. connection state of fb1 and fb2 pins sw state remarks connected to an external resistor sw1 : on sw2 : off the dc/dc output voltage can be set freely by the exter- nal resistor connected to cvblpf pin (pin 7) sw1 : off sw2 : on the external resistor for out put voltage setting is unnec- essary because dc/dc output voltage setting resistor embedded in the ic is used. set vo1 = 1.23 v, vo2 = 3.45 v. 3 error comp. intref 2.5 v + ? ? + fb1 sw1 comp.1 sw2 4 10 11 fb2 vo1 vo2 < vo control >.
mb39a138 ds04?27270?1e 15 (8) over-temperature protec tion circuit block (otp) if the junction temperature reaches + 150 c, the over-temperature protection circuit block makes the dis- charge function internal in the ic operate and make s voltage output of both channels stop. the soft start activates again when the junction temperature goes down to + 125 c. (9) output block (drv1, drv2) the output circuit is configured in cmos type for both of the high-side and the low-side, allowing the external n-ch mos fet to drive. (10) over current detection block (ilim) the over current detection block (ilim) compares the difference voltage between the pgnd pin (pin 18) and the lx1 pin (pin 22) during the synchronous rectificati on period with the ilim1 pin (pin 5) voltage, and compares the difference voltage between the pgnd pin and the lx2 pin (pin 16) with the ilim2 pin (pin 9) voltage, and detects over current at each cycle. the high-side fet remains the off st ate until the voltage difference be tween the pgnd pin and the lxx pin becomes below the ilimx pin voltage and on in the high-side fet is allowed after the voltage difference has been below the ilimx pin voltage. this protects a circuit from flowing over current. this protection operates to drop the output voltage. the difference voltage between pgnd and lxx caused during the synchronous rectification period is de- scribed as the voltage waveform by sensing the induct or current, as the on-resistance of the low-side fet is regarded as the sense resistor. the optional limit value for over current can be set by setting a resistor to the ilimx pin because i ilim current which is 10 a (typ) is supplied from the ilimx pin. as for i ilim current, the temperature slope which is 4200 ppm/ c is set to compensate the temperature dependence ch aracteristics of the low-side fet on-resistance. note: x is each channel number. (11) control block (ctl) on and off for ch1 is set by the ctl1 pin (pin 1) and on and off for ch2 is set by the ctl2 pin (pin 8). if setting ctl1 and ctl2 to "l" level at the same time, th is ic turns to the standby state. (the maximum power- supply current at standby is 10 a.) control function table ctl1 ctl2 dc/dc converter (ch1) dc/dc converter (ch2) ll off off h l on off lh off on h h on on
mb39a138 16 ds04?27270?1e protection function table the following table shows the state of drvh1, drvh2 pins (pin 23, pin 15) and drvl1, drvl2 pins (pin 21, pin 17) when each protec tion function operates. note: x is each channel number. protection function detection condition output of each pin after detection dc/dc output dropping operation vb drvhx drvlx under voltage lockout protection (uvlo) v cvblpf < 3.6 v ? ll electrical discharge by discharge function under voltage protection (uvp) v fbx < intrefx 0.7 v 5.2 v l l electrical discharge by discharge function over voltage protection (ovp) v fbx > intrefx 1.15 v 5.2 v l h 0 v clamping over current protection (ilim) v pgndx ? v lxx > v ilimx 5.2 v switching switching the voltage is dropped by the constant current over temperature protection (otp) tj > + 150 c 5.2 v l l electrical discharge by discharge function control (ctl) ctlx : h l (vox > 0.2 v) 5.2 v l l electrical discharge by discharge function
mb39a138 ds04?27270?1e 17 i/o pin equivalent circuit diagram (continued) gnd ctl1, ctl2 vcc 0.1 v + ? cvblpf c s 1, c s 2 gnd gnd cvblpf fb1, fb2 2.5 v + ? gnd vo1, vo2 cvblpf gnd gnd cvblpf ilim1, ilim2 20 1, 8 6 3 ,11 5,9 7 2,12 4,10 fb1, fb2 pins vo1, vo2 pins ctl1, ctl2 pins cs1, cs2 pins ilim1, ilim2 pins cvblpf pin esd protection element
mb39a138 18 ds04?27270?1e (continued) gnd cvblpf te s t lx1, lx2 drvh1, drvh2 cb1, cb2 pgnd vb drvl1, drvl2 pgnd vb vcc pgnd vb cb1, cb2 1 3 24,14 2 3 ,15 22,16 19 21,17 1 8 drvl1, drvl2 pins vb pin test pin drvh1, drvh2, cb1, cb2 and lx1, lx2 pins
mb39a138 ds04?27270?1e 19 example application circuit vb te s t 7 1 3 4 3 1 5 2 10 11 8 9 12 6 cvblpf vb vcc vcc vo1 vcc vo2 12 v 1.2 v, 5 a 3 . 3 v, 5 a c7 c 8 c1-1 c1-2 c2- 3 c2-1 c 3 -2 c 3 -1 c6 c4- 3 c4-1 vo1 c9 r7 fb1 ilim1 ctl1 ctl1 r2 r5 r4 r6 c1 3 c12 r1-2 r1-1 c s 1 vo2 fb2 ctl2 ctl2 ilim2 c s 2 gnd vb vcc 20 19 vb pgnd vin d2 d1 7 g g 2 q1 s 1 8 d2 c5 l1 d1 5 4 q1 s 3 6 24 2 3 22 21 14 15 16 17 1 8 cb1 lx1 crvh1 drvl1 cb2 drvh2 drvl2 lx2 pgnd l2 g d2 d1 7 2 q 3 s 1 8 g d2 d1 5 4 q 3 s 3 6 r 3 -2 r 3 -1 mb 3 9a1 38
mb39a138 20 ds04?27270?1e parts li st nec : nec electronics corporation sanyo : sanyo electric co., ltd. tdk : tdk corporation ssm : susumu co., ltd. koa : koa corporation compo- nent item specification vendor package part number remarks q1 n-ch fet vds = 30 v, id = 8 a, ron = 21 m ? nec so-8 pa2755 dual type (2 elements) q3 n-ch fet vds = 30 v, id = 8 a, ron = 21 m ? nec so-8 pa2755 dual type (2 elements) l1 inductor 1.5 h (6.8 m ? , 9.0 a) tdk ? vlf10045t-1r5n9r0 l2 inductor 2.2 h (10.2 m ? , 7.4 a) tdk ? vlf10045t-2r2n7r4 c1-1 ceramic capacitor 10 f (25 v) tdk 3216 c3216jb1e106k c1-2 ceramic capacitor 10 f (25 v) tdk 3216 c3216jb1e106k c2-1 os-con 220 f (6.3 v, 15 m ? max) sanyo c6 6svpc220mv c2-3 ceramic capacitor 1000 pf (50 v) tdk 1608 c1608ch1h102j c3-1 ceramic capacitor 10 f (25 v) tdk 3216 c3216jb1e106k c3-2 ceramic capacitor 10 f (25 v) tdk 3216 c3216jb1e106k c4-1 os-con 220 f (6.3 v, 15 m ? max) sanyo c6 6svpc220mv c4-3 ceramic capacitor 1000 pf (50 v) tdk 1608 c1608ch1h102j c5 ceramic capacitor 0.1 f (50 v) tdk 1608 c1608jb1h104k c6 ceramic capacitor 0.1 f (50 v) tdk 1608 c1608jb1h104k c7 ceramic capacitor 0.1 f (50 v) tdk 1608 c1608jb1h104k c8 ceramic capacitor 2.2 f (16 v) tdk 1608 c1608jb1c225k c9 ceramic capacitor 1.0 f (16 v) tdk 1608 c1608jb1c105k c12 ceramic capacitor 0.015 f (50 v) tdk 1608 c1608jb1h153k c13 ceramic capacitor 4700 pf (50 v) tdk 1608 c1608jb1h472k r1-1 resistor 1 k ? ssm 1608 rr0816p102d r1-2 resistor 24 k ? ssm 1608 rr0816p243d r2 resistor 36 k ? ssm 1608 rr0816p363d r3-1 resistor 1.1 k ? ssm 1608 rr0816p112d r3-2 resistor 22 k ? ssm 1608 rr0816p223d r4 resistor 36 k ? ssm 1608 rr0816p363d r5 resistor 18 k ? ssm 1608 rr0816p183d r6 resistor 18 k ? ssm 1608 rr0816p183d r7 resistor 5.6 ? koa 1608 rk73h1jttd5r6f
mb39a138 ds04?27270?1e 21 application note 1. setting operating conditions setting output voltages 1. when the output setting voltag es are vo1 = 1.23 v, vo2 = 3.45 v: they can be set by the internal preset function. in this case, the smallest number of parts is required for the setting, as it is not necessary to us e a resistor to set the output voltage. 2. when the output setting voltages are other vo1 = 1.23 v, vo2 = 3.45 v: they can be set by adjusting the ratio of the output volt age setting resistor value. the output setting voltage is calculated by the following formula. the output ripple voltage value ( ? v ox ) is calculated by the following formula. note: x is each channel number. when not using the following feedback capacitor (cfb), select a resistor value that achieves r1//r2 15 k ? as a target. set so that the on-time (t on ) is more than 100 ns. (for how to calculate the on-time, see (4) on/off time generator block in ? function?) pin connection output voltage setting value (vo) ch1 fb1 = cvblpf vo1 = 1.23 v ch2 fb2 = cvblpf vo2 = 3.45 v v ox = r1 + r2 intref + ? v ox r2 2 v ox : output setting voltage [v] intref : internal reference voltage (ch1/ch2 : 0.7 v/2.0 v) ? v ox : output ripple voltage value [v] ? v ox = esr v in ? v ox v ox lv in f osc ? v ox : output ripple voltage value [v] l : inductor value [h] v in : power supply voltage [v] v ox : output setting voltage [v] f osc : oscillation frequency [hz] (c h1 : 310 khz, ch2 : 465 khz) r1 v ox r2 vo x fb x
mb39a138 22 ds04?27270?1e as the output voltage gets higher, the resistor value rati o of output voltage setting is getting higher. moreover, the oscillation frequency may become unstable as a re sult. this occurs becaus e the value of the ripple voltage applied to the fb pin is reduced by the r1/r2 ra tio. in this case, a stable oscillation frequency can be achieved by increasing the output ripple voltage or adding a capacitor (c fb ) in parallel to r1. select an additional capacitor using the following formula as a guide. moreover, adding a capacitor increases the output vo ltage according to the output ripple voltage. the following formula is used to calculate th e output voltage value to be increased. use the following formula to calculate the output se tting voltage when consideri ng the output setting voltage offset value. note: x is each channel number. c fb 10 (r1 + r2) 2 fosc r1 r2 c fb : capacitor value of feedback capacitor [f] r1, r2 : output voltage setting resistor value [ ? ] f osc : oscillation frequency [hz] vo_ offset = (v o ? intref) ? v o 2 intref vo_ offset : output setting voltage offset value [v] v o : output setting voltage [v] ? vo : output ripple voltage value [v] intref : internal reference voltage (ch1/ch2 : 0.7 v/2.0 v) v ox = r1 + r2 intref + ? v ox + v o_offset r2 2 v ox : output setting voltage[v] intref : internal reference vo ltage (ch1/ch2 : 0.7 v/2.0 v) ? v ox : output ripple voltage value [v] v o_offset : output setting voltage offset value [v] r1 v o r2 vo fb c fb ? vo vo_offset vo v t
mb39a138 ds04?27270?1e 23 consideration of output ripple voltage this device requires an output ripple voltage value as an operating principle. it must secure about 15 mv at the fb pin. calculate the output ripple voltage requir ed for the output of the dc/dc converter by the following formula. a stable oscillation frequency can be achieved by increasing the output ripple voltage. the output ripple voltage can be incr eased by selecting a larger output capacitor's esr or a smaller inductor value. however, if the output ripple voltage is increased ex cessively, the slope of the output ripple voltage during the off-period (t off ) becomes steeper, which affects the bottom detec tion voltage more. as a result, it affects the output voltage. this become prominent, if it increa se on-duty. ensure that the ripple voltage at the fb pin is not excessively large. ? v ox k 15 mv ? v ox : output ripple voltage value [v] k : coefficient when c fb is used : k = 1; c fb is not used : k = v o intref v o : output setting voltage [v] intref : internal reference vo ltage (ch1/ch2 : 0.7 v/2.0 v)
mb39a138 24 ds04?27270?1e setting soft-start time calculate the soft-start time by the following formula. calculate the delay time until the soft-sta rt activation by the following formula. in almost all cases, no delay time is generated when the soft-start activates in the state that one side channel has already activated (uvlo release: vb output already). note : set the slew rate of 750 v/s or more to the input-signal to ctl1 and ctl2 pins. t s = intref c cs 5 10 ? 6 t s : soft-start time [s] (t ime until output reaches 100%) intref : internal reference voltage (ch1/ch2 : 0.7 v/2.0 v) c cs : cs pin capacitor value [f] t d = 30 (c vb + c cvblpf ) t d : vb voltage delay time [s] c vb : vb capacitor value [f] c cvblpf : cvblpf capacitor value [f] 0 50 100 150 200 250 300 350 400 510152025 c vb = 2.2 f, c cvblpf = 1 f reference characteristics : time until the so ft-start activates vs. power supply voltage power supply voltage v in [v] time until the soft-start activates td [ s] ctl1 ctl2 v o 1 v o 2 t s1 t d1 t s2
mb39a138 ds04?27270?1e 25 setting over current detection value the over current detection value can be set by adjusti ng the over current detection resistor value connected to the ilim pin. calculate the resistor value by the following formula. if the rate of inductor saturation current is small, the inductor value decreases and the ripple current of inductor increase when the over-current flows. at that time there is a possibility that the limited output current increases or is not limited, because th e bottom of inductor current is detec ted. it is necessary to use the inductor that has enough large rate of inductor saturation current to prevent the overlap current. r on_sync (i lim ? ? il + v o 260 10 ? 9 ) r lim = 2l 10 10 ? 6 r lim : over current detection value setting resistor [ ? ] i lim : over current detection value [a] ? il : ripple current peak-to-peak value of inductor [a] r on_sync : on resistance of low-side fet [ ? ] v o : output setting voltage [v] l : inductor value [h] ilim r lim ? i l i o i lim 0 inductor current value to limit over current time
mb39a138 26 ds04?27270?1e the over current limit value is affected by ilim pin source current and over current detection offset voltage in the ic except for the on resist ance of the low-side fet and the indu ctor value. the variation of dropped over current limit value caused by ic characteri stics is calculated by the following formula. the over current detection value needs to set a su fficient margin against the maximum load current. ? i lim = ? 1.7 10 ? 6 r lim + 0.02 r on_sync ? i lim : the variation of dropped over current limit value [a] r lim : resistor to set over current limit [ ? ] r on_sync : low-side fet on resistance [ ? ] ? i lim i o 0 i lim i lim ? inductor current over current limit value time dropped over current limit value due to ic's characteristics
mb39a138 ds04?27270?1e 27 vb regulator in the condition for which the potential difference betwe en vcc and vb is insufficient, the decrease in the voltage of vb happens because of powe r output on-resistance and load curr ent (mean current of all external fet gate driving current and load current of internal ic) of the vb regulator. stop the switching operation when the voltage of vb decreases and it reaches thre shold voltage (vthl) of the under voltage lockout protection circuit. therefore, set oscillation frequency or external fet or i/o potential difference of the vb regulator using the following formula as a target when you use this ic. w hen using it in the condition for which the i/o potential difference is insufficient, check the operation on an act ual device carefully during normal operation, startup and shutdown. power dissipation and the thermal design as for this ic, considerations of the power dissipatio n and thermal design are not necessary in most cases because of its high efficiency. however, they are necessary for the use at the conditions of a high power supply voltage, a high oscillation frequency, high load, and the high temperature. calculate ic internal loss by the following formula. calculate junction temperature (tj) by the following formula. v in vb ( vthl ) + (qg f osc + i cc ) r vb vb ( vthl ) : threshold voltage of under-vo ltage lockout protection circuit = 3.8 [v] max qg : total amount of gate c harge of external fet [c] f osc : oscillation frequency [hz] i cc : power supply current = 2 10 ? 3 [a] ( load current of vb (ldo)) r vb : vb output on-resistance = 75 [ ? ] (the reference value at v in = 6 v) p ic = v cc (i cc + q g1 f osc1 + q g2 f osc2 ) p ic : ic internal loss [w] v cc : power supply voltage (v in ) [v] i cc : power supply current [a] (2 ma max) q g1 , q g2 : total quantity of charge for the hi gh-side fet and the low-side fet of each ch [c] (total at vgs = vb) f osc1 , f osc2 : oscillation frequency of each ch [hz] t j = t a + ja p ic t j : junction temperature [ c] ( + 125 c max) t a : operation ambient temperature [ c] ja : tssop-24 package thermal resistance ( + 75 c/w) p ic : ic internal loss [w]
mb39a138 28 ds04?27270?1e 2. selecting parts selection of smoothing inductor the inductor value selects the value that the ripple curr ent peak-to-peak value of the inductor is 50% or less of the maximum load current as a ro ugh standard. calculate the inductor va lue in this case by the following formula. it is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the inductor is a rated value or less. calculate the maximum current value of the inductor by the following formula. l v in ? v o v o lor i omax v in f osc l : inductor value [h] i omax : maximum load current [a] lor : ripple current peak-to-peak value of inductor / maximum load current ratio (=0.5) v in : power supply voltage [v] v o : output setting voltage [v] f osc : oscillation frequency [hz] i lmax i omax + ? il 2 ? il = v in ? v o v o lv in f osc i lmax : maximum current value of inductor [a] i omax : maximum load current [a] ? il : ripple current peak-to-peak value of inductor [a] l : inductor value [h] v in : power supply voltage[v] v o : output setting voltage[v] f osc : oscillation frequency [hz] i omax i lmax 0 ? i l inductor current time
mb39a138 ds04?27270?1e 29 selection of switching fet select the low-side fet on resistance from the below range in order to op erate the over current limit function normally. the maximum value of the current that flows to the sw itching fet must be calculated in order to determine whether the current flowing to the switching fet is within the rated value. calculate the maximum value of the current that flows to the switching fet by the following formula. moreover, it is necessary to calculate the loss of switching fet to judge whether a power dissipation of switching fet is a rated value or less. calculate th e loss on high-side fet by the following formula. high-side fet conduction loss high-side fet switching loss 0.03 r on_sync 0.2 (i lim ? ? il ) (i lim ? ? il ) 22 r on_sync : low-side fet on resistance [ ? ] ? il : ripple current peak-to-peak value of inductor [a] i lim : over current detection value [a] i d = i omax + ? il 2 i d : drain current [a] i omax : maximum load current [a] ? il : ripple current peak-to-peak value of inductor [a] p mainfet = p ron_main + p sw_main p mainfet : high-side fet loss [w] p ron_main : high-side fet conduction loss [w] p sw_main : high-side fet switching loss [w] p ron_main = i omax 2 v o r on_main v in p ron_main : high-side fet conduction loss [w] i omax : maximum load current[a] v in : power supply voltage[v] v o : output voltage[v] r on_main : high-side fet on resistance [ ? ] p sw_main = v in f osc (i btm t r + i top t f ) 2 p sw_main : switching loss [w] v in : power supply voltage [v] f osc : oscillation frequency (hz) i btm : ripple current bottom value of inductor [a] i top : ripple current top value of inductor [a]
mb39a138 30 ds04?27270?1e t r : turn-on time on high-side fet [s] t f : turn-off time on high-side fet [s] t r and t f is calculated by the following formula. the loss of the low-side fet is calculated by the following formula. (the transition voltage of the voltage between drain and source on low-side fet is generally small, and the switching loss is omitted here for the small one as it is possible to disregard it.) the gate drive power of switching fet is supplied by ld o in ic, therefore all of the allowable maximum total gate charge (qgtotalmax) of all switching fet fo r 2 channels is calculated by the following formula. i btm = i omax ? ? il , i top = i omax + ? il 22 ? il : ripple current peak-to-peak value of inductor [a] i omax : maximum load current [a] t r = q gd 4 , t f = q gd 1 v b ? v gs (on) v gs (on) q gd : quantity of charge between ga te and drain on high-side fet [c] v gs (on) : voltage between gate and s ources in qgd on high-side fet [v] v b : vb voltage [v] p syncfet = r ron_sync = i omax 2 (1 ? v o ) r on_sync v in p ron_sync : low-side fet conduction loss [w] i omax : maximum load current [a] v in : power supply voltage [v] v o : output voltage [v] r on_sync : low-side fet on-resistance [ ? ] qg to t a l m a x 140000 f osc2 qg totalmax : all of the allowable maximum total gate charge of all switching fet for 2 channels [nc] f osc2 : ch2 oscillation frequency [khz]
mb39a138 ds04?27270?1e 31 selection of fly-back diode fly-back diode is not needed in g eneral. however, it is possible to enhance the conversion efficiency by building in the fly-back diode, thought it is usually un necessary. the effect is achieved in the condition where the oscillation frequency is high or output voltage is lowe r. select schottky barrier diode (sbd) that the forward current is as small as possible. in this dc/dc control ic, the period for the electric current flows to fly-back diode is limited to synchronous rectification period (1 20 [ns]) because of using the synchronous rectification method. therefore, select the one that the electric curre nt of fly-back diode does not exceed ratings of forward current surge peak (i fsm ).calculate the forward current surge peak ratings of fly-back diode by the following formula. calculate ratings of the fly-back diode by the following formula: selection of output capacitor a certain level of esr is required for stable operation of this ic. use a tantalum capacitor or polymer capacitor as the output capacitor. if using a ce ramic capacitor with low esr, a resi stor should be connected in series with it to increase esr equivalently. calculate the required esr for the smoothi ng capacitor by the following formula. select the capacitance of the output capacito r with the following condition to a target. when using a capacitor where the capacity demanded by the above formula is unfulfilled, use it after intensively operation check that there is no problem with the jitter level. i fsm i omax + ? il 2 i fsm : forward current surge peak ratings of sbd [a] i omax : maximum load current [a] ? il : ripple current peak-to-peak value of inductor [a] v r_fly > v in v r_fly : reverse voltage of fly-back diode direct current [v] v in : power supply voltage [v] esr ? il ? v o esr : series resistance of output capacitor [ ? ] ? v o : output ripple voltage [v] ? il : ripple current peak-to-peak value of inductor [a] c o 1 4 f osc esr c o : output capacitor value [f] f osc : oscillation frequency [hz] esr : series resistance of output capacitor [ ? ]
mb39a138 32 ds04?27270?1e moreover, the output capacitor values are also derived from the allowable amount of overshoot and under- shoot. the following formula is represented as the wors t condition in which the sh ift time for a sudden load change is 0s. for a longer shift time, the smaller am ount of output capacitor is acceptable than the value calculated by the following formula. overshoot condition undershoot condition the capacitor has frequency, operating temperature, and bi as voltage characteristics, etc. therefore, it must be noted that its effective capacitor value may be significantly smaller, depending on the use conditions. calculate voltage rating of the output capacitor by the following formula. capacitor voltage rating should have a suffic ient margin to withstand the output voltage. calculate the allowable ripple current of th e output capacitor by the following formula. c o ? i o 2 l 2 v o ? v o_over c o ? i o 2 l (v o + v in f osc 380 10 9 ) 2 v o ? v o_under (v in ? v o ? v in f osc 380 10 9 ) c o : output capacitor value [f] ? v o_over : allowable amount of output voltage overshoot [v] ? v o_under : allowable amount of output voltage undershoot [v] ? i o : current difference in sudden load change [a] l : inductor value [h] v in : power supply voltage [v] v o : output setting voltage[v] f osc : oscillation frequency [hz] v co > v o v co : withstand voltage of the output capacitor [v] v o : output voltage [v] irms ? il 2 irms : allowable ripple current (effective value) [a] ? il : ripple current peak-to-peak value of inductor [a] 3
mb39a138 ds04?27270?1e 33 selection of input capacitor select the input capacitor whose esr is as small as possible. the cera mic capacitor is an ideal. use the tantalum capacitor and the polymer capacitor of t he low esr when a mass capacitor is needed as the ceramic capacitor can not support. if a inductor is connected as a nois e filter between the power supply and the input capacitor, and the cut-off frequency for this inductor and input capacitor is set to a value lower than the oscillation frequency, the ripple voltage by the switching operat ion of dc/dc is generated. discuss the lower bound of input capacitor according to an allowable ripple voltage. calculate the ripple voltage of the power supply from the following formula. capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc. the effective capacitor value might become extr emely small depending on the use conditions. note the effective capacitor value in the use conditions. calculate ratings of the input capacitor by the following formula: select the capacitor voltages rating with withstand voltage with margin enough for the input voltage. in addition, use the allowable ripple current with an e nough margin, if it has a rating. calculate an allowable ripple current by the following formula. ? v in = i omax v o + esr (i omax + ? il ) c in v in f osc 2 ? v in : power supply ripple voltage peak-to-peak value [v] i omax : maximum load current value [a] c in : input capacitor value [f] v in : power supply voltage [v] v o : output setting voltage [v] f osc : oscillation frequency [hz] esr : series resistance component of input capacitor [ ? ] ? il : ripple current peak-to-peak value of inductor [a] v cin > v in v cin : withstand voltage of the input capacitor [v] v in : power supply voltage [v] irms i omax v in irms : ripple current (effective value) [a] i omax : maximum load current value [a] v in : power supply voltage [v] v o : output setting voltage [v] v o (v in ? v o )
mb39a138 34 ds04?27270?1e selection of boot strap capacitor to drive the gate of high-side fet, the bootstrap capacitor must have enough stored charge. therefore, a minimum value as a target is assumed the capacitor wh ich can store electric charge 10 times that of the qg on high-side fet. and sele ct the boot strap capacitor. calculate ratings of the boot strap capacitor by the following formula: vb pin capacitor 2.2 f is assumed to be a standard, and when qg of switch ing fet used is large, it is necessary to adjust it. to drive the gate of high-side fet, the bootstr ap capacitor must have enough stored charge. therefore, a minimum value as a target is assumed the capacitor value which can store electric charge 100 times that of the qg on switching fet. and select it. moreover, capacitor change may cause an overshoot when ctl was turned on. although the overshoot does not affect dc/dc operati on, check that the vb pin does not exceed its rating before applying the capacitors. calculate ratings of the vb pin capacitor by the following formula: cvblpf pin capacitor and resistor lpf to power supply from the vb regulator (vb pin) to the control system power supply (cvblpf pin) is made by the cvbpf pin's capacitor and the resistor between the vb pin and the cvbpf pin. the cut-off frequency is set to one tenth of oscillation frequency as a target (1 f is the standard of the capacitor value). select as small a value as possible (the recommended value is about 5 ? ). because the voltages drop to the control system powe r supply is occurred when setting the resistor value to extremely large value. c boot 10 q g v b c boot : boot strap capacitor value [f] q g : amount of gate charge on high-side fet [c] v b : vb voltage [v] v cboot > v b v cboot : withstand voltage of the boot strap capacitor[v] v b : vb voltage [v] c vb 100 qg v b c vb : vb pin capacitor value [f] q g : total amount of gate charge of hi gh-side fet and low-side fet for 2ch [c] v b : vb voltage [v] v cvb > v b v cvb : withstand voltage of the vb pin capacitor [v] v b : vb voltage [v]
mb39a138 ds04?27270?1e 35 3. layout consider the points listed below and do the layout design. provide the ground plane as much as possible on the ic mounted face. connect bypass capacitor con- nected with the vcc and vb pins, and gnd pin of the switching system parts with switching system gnd (pgnd). connect other gnd connection pins with control system gnd (agnd), and separate each gnd, and try not to pass the heavy current path through the control system gnd (agnd) as much as possible. in that case, connect control syst em gnd (agnd) and switching system gnd (pgnd) at the single point of gnd (pgnd) in ic. connect the switching system parts as much as possible on the surface. avoid the connection through the through-hole as much as possible. as for gnd pins of the switching system parts, provide the through hole at the proximal place, and connect it with gnd of internal layer. pay the most attention to the lo op composed of input capacitor (c in ), switching fet, and fly-back diode (sbd). consider making the current loop as small as possible. place the boot strap capacitor (c boot1 , c boot2 ) proximal to cbx and lxx pins of ic as much as possible. large electric current flows momentary in the net of drvhx and drvlx pins connected with the gate of switching fet. wire the linewidth of about 0.8 mm to be a standard, as short as possible. by-pass capacitor (c vblpf , c vcc , c vb ) connected with cvblpf, vcc, and vb should be placed close to the pin as much as possible. also connect the gnd pin of the bypass capacitor with gnd of internal layer in the proximal through-hole. pull the feedback line to be connected to the vox pin of the ic separately from near the output capacitor pin, whenever possible, in order to feed back it to th e ic more accurately. it is the ripple voltage which is generated from esr of the output capacitor. consider the net connected with vox and fbx pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. moreover, place the output voltage setting resistor c onnected with this net clos e to the ic as much as possible, and try to make the net as short as possible. in addition, for the internal layer right under the component mounting place, provide the control syst em gnd (agnd) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible. switching system parts : input capacitor (c in ), switching fet, fly-back diode (sbd), inductor (l), output capacitor (c o ) agnd pgnd agnd 1pin pgnd c boot1 c boot2 c vb c vcc c vref c in c o s bd (option) v in c in c o pgnd s bd (option) vo1 vo2 l l layout example of ic peripheral layout example of switching system parts through-hole connect agnd and pgnd right under ic surface internal layer high-side fet to the lx1 pin low-side fet low-side fet high-side fet through-hole output voltage vo1 feedback output voltage vo2 feedback to the lx2 pin output volt- age setting resistor lay- out
mb39a138 36 ds04?27270?1e reference data (continued) conversion efficiency vs. load current conversion efficiency vs. load current conversion efficiency (%) conversion efficiency (%) load current i o (a) load current i o (a) oscillation frequency vs. load current oscillation frequency vs. load current oscillation frequency fosc (khz) oscillation frequency fosc (khz) load current i o (a) load current i o (a) output voltage vs. load current output voltage vs. load current output voltage v o (v) output voltage v o (v) load current i o (a) load current i o (a) 50 60 70 8 0 90 100 012 3 4 5 v in =12 v v o1 =1.2 v t a = +25c 50 60 70 8 0 90 1 00 012 3 4 5 v in = 12 v v o2 = 3 . 3 v t a = +25c 190 250 3 10 3 70 4 3 0 012 3 45 v in =12 v v o1 =1.2 v t a = +25c 3 40 400 460 520 5 8 0 012 3 45 v in = 12 v v o2 = 3 . 3 v t a = +25c 1.10 1.15 1.20 1.25 1. 3 0 012 3 45 v in = 12 v v o1 = 1.2 v t a = +25c 3 .00 3 .15 3 . 3 0 3 .45 3 .60 012 3 45 v in = 12 v v o2 = 3 . 3 v t a = +25c
mb39a138 ds04?27270?1e 37 (continued) i o1 : 2 a/div 100 s /div 5 a 0 a v in = 12 v, v o1 = 1.2 v, s r s et = 0.75 a/ s i o2 = 0 a 5 a, t a = + 25 c v o1 : 50 mv/div 4 1 v in = 12 v, v o2 = 3 . 3 v, s r s et = 0.75 a/ s i o2 = 0 a 5 a, t a = + 25 c 100 s /div v o2 : 50 mv/div i o2 : 2 a/div 5 a 0 a 1 4 1 2 v in = 12 v, v o1 = 1.2 v, i o1 = 5 a, v o2 = 3 . 3 v, i o2 = 5 a, t a = + 25 c v o1 : 50 mv/div (ac) v o2 : 50 mv/div (ac) 2.0 s /div ctl1 : 5 v/div v in = 12 v, v o1 = 1.2 v, i o1 = 5 a (0.24 ? ), v o1 : 500 mv/div v lx1 : 10 v/div 1 m s /div 1 4 2 v in = 12 v, v o2 = 3 . 3 v, i o2 = 5 a (0.66 ? ), ctl2 : 5v/div v o2 : 1v/div v lx2 : 10v/div 1 m s /div 1 4 2 ripple waveform ch1 load sudden change waveform ch2 load sudden change waveform ch1 ctl startup waveform ch2 ctl startup waveform softstart setting time = 2.1 ms, ta = + 25 c softstart setting time = 1.9 ms, ta = + 25 c
mb39a138 38 ds04?27270?1e (continued) 3 1 2 ctl1 : 5 v/div 100 s /div v o1 : 500 mv/div v lx1 : 10 v/div v in = 12 v, v o1 = 1.2 v, i o1 = 5 a (0.24 ? ), t a = + 25 c 3 1 2 100 s /div ctl2 : 5 v/div v o2 : 1 v/div v lx2 : 10 v/div v in = 12 v, v o2 = 3 . 3 v, i o2 = 5 a (0.66 ? ), t a = + 25 c 3 4 2 v in = 12 v , v o1 = 1.2 v , t a = + 25 c v lx1 : 10 v / div l o1 : 10 a / div v o1 : 500 mv / div 500 s / div 3 4 2 v in = 12 v , v o2 = 3 . 3 v , t a = + 25 c v lx2 : 10 v / div l o2 : 10 a / div v o2 : 1 v / div 500 s / div ch1 ctl shutdown waveform ch2 ctl shutdown waveform ch1 output over current waveform ch2 output over current waveform normal operation over current protection under voltage protection normal operation over current protection under voltage protection
mb39a138 ds04?27270?1e 39 usage precaution 1. do not configure the ic over the maximum ratings. if the ic is used over the maximum ratings, the lsi may be permanently damaged. it is preferable for the device to normally operate within the recommended usa ge conditions. usage outside of these conditions can have an adverse effect on the reliability of the lsi. 2. use the device within the recommended operating conditions. the recommended values guarantee the normal lsi ope ration under the recomm ended operating conditions. the electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item. 3. printed circuit board ground lines should be set up with consideration for common impedance. 4. take appropriate measures against static electricity. containers for semiconductor materials should have anti -static protection or be made of conductive ma- terial. after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. work platforms, tools, and instruments should be properly grounded. working personnel should be gro unded with resistance of 250 k ? to 1 m ? in serial body and ground. 5. do not apply negative voltages. the use of negative voltages below ? 0.3 v may make the parasitic transistor activated to the lsi, and can cause malfunctions. ordering information ev board ordering information rohs compliance information of lead (pb) free version the lsi products of fujitsu microelectronics with ?e1? are compliant with rohs directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (pbb) , and polybrominated diphenyl ethers ( pbde) . a product whose part number has trailing characters ?e1? is rohs compliant. part number package remarks mb39a138pft- ??? e1 24-pin plastic tssop (fpt-24p-m10) lead free version ev board number ev board version no. remarks mb39a138evb-01 mb39a138evb-01 rev.2.0 tssop-24
mb39a138 40 ds04?27270?1e marking format (lead free version) xxxx 39a138 xxx e1 index lead free version
mb39a138 ds04?27270?1e 41 labeling sample (lead free version) 2006/03/01 assembled in japan g qc pass (3n) 1mb123456p-789-ge1 1000 (3n)2 1561190005 107210 1,000 pcs 0605 - z01a 1000 1/1 1561190005 mb123456p - 789 - ge1 mb123456p - 789 - ge1 mb123456p - 789 - ge1 pb lead-free mark jeita logo jedec logo the part number of a lead-free product has the trailing characters ?e1?.
mb39a138 42 ds04?27270?1e mb39a138pft- ??? e1 recommended conditions of moisture sensitivity level [fujitsu microelectronics recommended mounting conditions] [mounting conditions] (1) ir (infrared reflow) (2) manual soldering (partial heating method) temperature at the tip of an soldering iron: 400 c max time: five seconds or below per pin item condition mounting method ir (infrared reflow) , m anual soldering (partial heating method) mounting times 2 times storage period before opening please use it within two years after manufacture. from opening to the 2nd reflow less than 8 days when the storage period after opening was exceeded please process within 8 days after baking (125 c, 24h) storage conditions 5 c to 30 c, 70 % rh or less (the lowest possible humidity) 260 c (e) (d') (d) 255 c 170 c 190 c rt ( b ) ( a ) (c) to note: temperature : on the top of the package body ?h? level : 260 c max (a) temperature increase gradient : average 1 c/s to 4 c/s (b) preliminary heating : temperature 170 c to 190 c, 60 s to 180 s (c) temperature increase gradient : average 1 c/s to 4 c/s (d) peak temperature : temperature 260 c max; 255 c or more, 10 s or less (d?) main heating : temperature 230 c or more, 40 s or less or temperature 225 c or more, 60 s or less or temperature 220 c or more, 80 s or less (e) cooling : natural cooling or forced cooling main heating
mb39a138 ds04?27270?1e 43 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 24-pin pl as tic t ss op le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 4.40 mm 7. 8 0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.20 mm max weight 0.10 g 24-pin pl as tic t ss op (fpt-24p-m10) (fpt-24p-m10) c 200 8 fujit s u microelectronic s limited f240 33s -c-1-1 7. 8 0 0.10(. 3 07 .004) 0.65(.026) (.17 3 .004) 4.40 0.10 6.40 0.20 (.252 .00 8 ) 0.10(.004) "a" index # # btm e-mark 1 12 24 1 3 0.22 .00 8 0.10(.004) .005 0.1 3 1.20(.047) (.004 .002) 0.60 0.15 (.024 .006) 0~ 8 ? det a il s of "a" p a rt ( s t a nd off) (mo u nting height) 0.10 0.05 max +0.07 +.00 3 ?0.02 ?.001 +0.06 +.002 ?0.0 3 ?.001 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 2) pin s width do not incl u de tie ba r c u tting rem a inder. note 3 ) #: the s e dimen s ion s do not incl u de re s in protr us ion.
mb39a138 fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and applicatio n circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of op erations and uses of fujitsu microelec tronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to us e based on such information. when you develop equipment incor - porating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectron ics warrant non-infringement of any third- party's intellectual property right or o ther right by using such information. fujitsu microelectronics assu mes no liability for any infringement of the intellectual propert y rights or other rights of third parties which would re sult from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, persona l use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury , severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersi ble repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against in jury, damage or loss from such failure s by incorporating safety design measures into your facility a nd equipment such as redundancy, fi re protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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